The present invention relates generally to fully automated scan testing flip-flops and more particularly to less complex fully automated scan testing flip-flops.
Application Specific Integrated Circuits (ASICS) can be programmed to perform any number of functions. In order to test them efficiently, it is important to include testability feature on the circuits that are independent of any potential programming. In this way, the same approach can be used to test a chip regardless of its eventual application. As a result, a design-for-testing (DFT) approach is commonly used in development of hardware components. Scan testing is a result of this approach. It provides for the control and observation of all state elements inside the design of an integrated circuit.
In order to implement scan testing, every flip-flop in a design must have an access method. The standard approach is to design a flip-flop that has a multiplexer at its main input and a control signal to switch between a test mode and a normal mode. In the normal mode the circuit operates as designed. In the test mode, the simplest case results in all of the flip-flops acting as one large shift register. This allows the insertion of test values into the circuit one at a time. At each clock step a bit is moved further along into the shift register chain. Eventually, the entire circuit is loaded with test values, and then the shift register unloaded at one end while new test values are loaded in at the other.
The multiplexed flip-flop approach has several inherent problems, the most important of which is its use of at least two different clocking schemes for the normal and test modes of operation. Because the timing in a high-speed circuit must be accurate to fractions of a nanosecond in order for the multiplexed flip-flop approach to work correctly, it is common for skew or overlap between clocks to cause data to jump across two flip-flops instead of the next one. This phenomenon, called shoot-through, causes the flip-flops to update in the wrong order and can invalidate the testing cycle.
Another problem occurs when attempting to verify that the circuit can operate at its required frequency, a process known as at-speed testing. Using a multiplexed flip-flop, the chip would be put into scan mode to load in all the values, switched to normal mode to operate for one cycle, then returned to scan mode in order to observe the results. This require that the multiplexer control signal change almost instantaneously across wide portion of a chip. Because it is very difficult to coordinate the clocking, control, and protocol signals to such fine precision, a different implementation for scan testing was sought. Software support for the multiplexed flip-flop was insufficient to overcome its shortcomings, so a hardware solution was developed, taking the form of a Fully Automated Scan Testing, or FAST, flip-flop.
The FAST flip-flop was designed specifically to alleviate the various timing problems of the multiplexed flip-flop. It had three advantages over the multiplexed flip-flop. The first was its utilization of two special, non-overlapping shift clocks, making the normal system clock unnecessary for shifting. Because the clocks were non-overlapping, skew was no longer problem and shoot-through could not occur. The clocks could vary significantly from one flip-flop to the next and still operate reliably. The second advantage was that the FAST flip-flop was capable of the at-speed testing without the difficulties associated with multiplexed flip-flops. Finally, FAST flip-flops supported a technique called partial scan, where some of the flip-flops were on the scan chain and others were not, so sections of the circuit could be scanned.
Although the FAST flip-flop had these significant advantages over the multiplexed flip-flop, it had several drawbacks. Its design took up about 75% more space on an integrated circuit chip because the additional testing circuitry in the FAST methodology required three latches instead of the two required for the multiplexed approach. It required the circuitry and routing space for three input signals instead of one. Also, due to the work inherent in the partial can technique, more time was required to create tests. When use of the partial scan technique was deemed unjustified a few years after the FAST flip-flop""s invention due to the inordinate amount of time required in the design process, a considerable portion of the FAST flip-flop""s chip area was being devoted to an unused feature.
The present invention provides an integrated circuit with a Fully Automated Scan Testing (FAST)-lite flip-flop. The integrated circuit has data, scan in, master-hold, clock, scan-into-master and master-to-scan-out inputs. A first transistor circuit is connected to the data, master-hold, and clock inputs and has a first output. A second transistor circuit is connected to the scan in and scan-into-master inputs and has a second output. A master latch is connected to the first and second outputs and has a master latch output. A third transistor circuit is connected to the second output and the master-to-scan-out and clock inputs and has a third output. A single slave latch is connected to the third switching circuit output and has a slave latch output. The FAST-lite flip-flop uses normal functionality master and slave latches to operate either in a normal mode or a test mode for scan testing. The FAST-lite flip-flop is so designated because it uses one less latch than the prior art and thus reduces the chip area require for its placement by about 20% over the original FAST design. This reduction in chip area also allows for faster normal operation of the integrated circuit as well as a decrease in testing time.
The present invention further provides an integrated circuit with a FAST-lite and/or FAST-lean flip-flops which make the integrated circuit design independent from the integrated circuit testing. The FAST-lite and/or FAST-lean flip-flops have the scan in input and scan out output ports separate from the normal data input port.
The present invention further provides an alternate embodiment with a FAST-lean flip-flop. The integrated circuit is similar to the FAST-lite, but merges the master-to-scan-out and clock inputs into a single merged signal which serves as a control for the slave latch. The FAST-lean flip-flop is so designated because it eliminates one input signal and its associated ports, circuitry, and wiring and so reduces the area and the routing congestion over the FAST-lite flip-flop.
The present invention further provides that the FAST, FAST-lite, and FAST-lean flip-flops are mutually compatible and may be incorporated in the same integrated circuit where old and new modules are mixed.
The present invention further provides an integrated circuit with a FAST-lite and/or FAST-lean flip-flops which have built-in testability.
The present invention further provides an integrated circuit with a FAST-lite and/or FAST-lean flip-flops which merge clocking schemes.
The present invention further provides an integrated circuit with a FAST-lite and/or FAST-lean flip-flops which scan into a slave latch.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.